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| Freescale Semiconductor Advance Information Document Number: MC33810 Rev. 4.0, 2/2008 Automotive Engine Control IC The 33810 is an eight channel output driver IC intended for automotive engine control applications. The IC consists of four integrated low side drivers and four low side gate pre-drivers. The low side drivers are suitable for driving fuel injectors, solenoids, lamps, and relays. The four gate pre-drivers can function either as ignition IGBT gate pre-drivers or as general purpose MOSFET gate predrivers. When configured as ignition IGBT gate pre-drivers, additional features are enabled such as spark duration, dwell time, and ignition coil current sense. When configured as a general purpose gate predriver, the 33810 provides external MOSFETs with short circuit protection, inductive flyback protection and diagnostics. The device is packaged in a 32 pin (0.65mm pitch) exposed pad SOIC. Features * Designed to operate over the range of 4.5V VPWR 36V * Quad ignition IGBT or MOSFET gate pre-driver with Parallel/SPI and/or PWM control * Quad injector driver with Parallel/SPI control * Interfaces directly to MCU using 3.3V / 5.0V SPI protocol * Injector driver current limit - 4.5A max. * Independent fault protection and diagnostics * VPWR standby current 10A max. * Pb-free packaging designated by suffix code EK VBAT 33810 ENGINE CONTROL EK SUFFIX (Pb-FREE) 98ARL10543D 32 PIN SOICW EP ORDERING INFORMATION Device PCZ33810EK/R2 Temperature Range (TA) -40C to 125C Package 32 SOICW-EP 33810 VDD VPWR VDD OUT0 OUT1 OUT2 OUT3 GND SCLK CS MISO ETPU ETPU ETPU ETPU GPIO ETPU ETPU ETPU SCLK CS SO DIN0 DIN3 GIN0 GIN3 OUT EN SPKDUR NOMI MAXI FB1 GD1 FB2 GD2 FB3 GD3 RSP RSN FB0 GD0 VBAT VBAT VBAT VBAT VBAT MCU MOSI SI VBAT VBAT VBAT Figure 1. MC33810 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006 - 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR VDD VDD ~50A VDD ~50A LOGIC CONTROL VPWR, VDD V8.0 Analog V2.5 Logic POR, Over-voltage Under-voltage Oscillator Bandgap Bias CS SI SCLK OUTEN ~15A VDD ~15A SPI INTERFACE V2.5 Outputs 0 to 3 SO DIN0 ~50A PARALLEL CONTROL Gate Control Current Limit Temperature Limit Short/Open + - ~50A lLimit VOC1 OUT0 OUT1 OUT2 OUT3 75A DIN1 RS DIN2 ~50A PWM CONTROLLER Exposed Pad + - DIN3 ~50A NOMI,MAXI DAC SPARK DURATION SPI SPI 100A VLVC + - GIN0 ~50A Open Secondary SPARK DAC ~50A + VPWR - FB0 FB1 FB2 FB3 GPGD Only GIN1 VOC GIN2 ~50A GATE DRIVE CONTROL Low V Clamp GPGD Clamp GIN3 ~50A VDD ~50A NOMI + - GD0 GD1 GD2 GD3 DAC SPKDUR MAXI + - RSP DAC RSN NOMI MAXI Exposed Pad GND Figure 2. 33810 Simplified Internal Block Diagram 33810 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT0 FB0 GD0 CS SCLK SI SO VDD OUTEN DIN0 DIN1 DIN2 DIN3 GD1 FB1 OUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OUT2 FB2 GD2 MAXI NOMI RSN RSP VPWR GIN0 GIN1 GIN2 GIN3 SPKDUR GD3 FB3 OUT3 GND Figure 3. 33810 Pin Connections Table 1. 33810 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 13. Pin Number 8 Pin Name VDD Pin Function Input Formal Name Digital Logic Supply Voltage Definition The VDD input supply voltage determines the interface voltage levels between the device and the MCU, and is used to supply power to the Serial Out buffer (SO), SPKDUR buffer, MAXI, NOMI, and pull-up current source for the Chip Select (CS). The SI input pin is used to receive serial data from the MCU. The SCLK input pin is used to clock in and out the serial data on the SI and SO pins, while being addressed by the CS. The Chip Select input pin is an active low signal sent by the MCU to indicate that the device is being addressed. This input requires CMOS logic levels and has an internal active pull-up current source. The SO output pin is used to transmit serial data from the device to the MCU. Active HIGH input control for injector outputs OUT0 - 3. The parallel input data is logically OR'd with the corresponding SPI input data register contents. These pins are the active HIGH input control for IGBT/General Purpose Gate Driver outputs 0 - 3. The parallel input data is logically OR'd with the corresponding SPI input data register contents in General Purpose Mode Only. 6 5 4 SI SCLK CS Input Input Input Serial Input Data Serial Clock Input Chip Select 7 SO Output Input Serial Output Data Driver Input 0, Driver Input 1, Driver Input 2, Driver Input 3 Gate Driver Input 0 Gate Driver Input 1 Gate Driver Input 2 Gate Driver Input 3 10, 11, 12, 13 DIN0,DIN1, DIN2,DIN3 24, 23, 22, 21 GIN0,GIN1, GIN2,GIN3 Input 20 SPKDUR Output Spark Duration Output This pin is the Spark Duration Output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed spark detection threshold. Analog Supply Voltage VPWR is the main voltage input for all internal analog bias circuitry. Ground This exposed pad is the only ground reference for analog, digital and power ground connections. 25 Exposed Pad (bottom of package) 9 VPWR GND Input Ground OUTEN Input Output Enable The Output Enable pin (OUTEN) is an active low input. When the OUTEN pin is low, the device outputs are active. The outputs are disabled when OUTEN is high. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33810 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 13. Pin Number 29 Pin Name MAXI Pin Function Output Formal Name Maximum Ignition Coil Current Definition This pin is the Maximum Ignition Coil Current output flag. This output is asserted when the IGBT Collector-Emitter current exceeds the selected level of the DAC. This signal also latches off the gate pre-drive outputs when configured as a General Purpose Gate pre-Driver. The MAXI current level is determined by the voltage drop across an external sense resistor connected to pins RSP and RSN. This pin is the Nominal Ignition Coil Current output flag. This output is asserted when the IGBT Collector-Emitter current exceeds the level selected by the DAC. In IGBT ignition gate pre-driver mode, these feedback inputs monitor the IGBT's collector voltage to provide the spark duration timer control signal. IGBT/General Purpose Gate pre-driver outputs are controlled by GIN0 GIN3. Pull-up and pull-down current sources are used to provide a controlled slew rate to an external IGBT or MOSFET connected as a low side driver. This pin is the Positive input of a current sense amplifier. This pin is the Negative input of a current sense amplifier. These pin are the Open drain low side injector driver outputs. 28 NOMI Output Nominal Ignition Coil Current Feedback Voltage Sense Gate Drive Output 2, 15, 31, 18 3, 14, 30,19 FB0 - FB3 GD0 -GD3 Input Output 26 27 RSP RSN Input Input Output Resistor Sense Positive Resistor Sense Negative Low Side Injector Driver Output 1, 16, 32, 17 OUT0 -OUT3 33810 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Ratings ELECTRICAL RATINGS VPWR Supply Voltage(1) VDD Supply Voltage(1) VPWR VDD VIL VIH VFB VOUTX VGDx ECLAMP -1.5 to 60 -1.5 to 60 -0.3 to 10 100 VDC VDC VDC mJ -1.5 to 45 -0.3 to 7.0 -0.3 to VDD VDC VDC VDC Symbol Value Unit SPI Interface and Logic Input Voltage (CS, SI, SO, SCLK, OUTEN, DIN0 - DIN3, GIN0 - GIN3, SPKDUR, NOMI, MAXI, RSP,RSN) IGBT/General Purpose Gate Pre-driver Drain Voltage (VFB0 to VFB3) Injector Output Voltage (OUTx) General Purpose Gate Pre-driver Output Voltage (GDx) Output Clamp Energy (OUT0 to OUT3)(Single Pulse) TJUNCTION = 150C, IOUT = 1.5A Output Clamp Energy (OUT0 to OUT3)(Continuous Pulse) TJUNCTION = 125C, IOUT = 1.0A (Max Injector frequency is 70Hz) Output Continuous Current (OUT0 to OUT3) TJUNCTION = 150C Maximum Voltage for RSN and RSP inputs Frequency of SPI Operation (VDD = 5.0V) ESD Voltage (2), (3) ECLAMP 100 mJ IOSSSS 2.0 A VRSX - VESD1 VESD2 VESD3 -0.3 - VDD 6.0 2000 200 750 VDC MHz V Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) THERMAL RATINGS Operating Temperature Ambient Junction2 Case Storage Temperature Power Dissipation (TA = 25C) Peak Package flow Temperature During Solder Mounting DWB Suffix EW Suffix Thermal Resistance Junction-to-Ambient Junction- to-Lead Junction-to-Flag C TA TJ TC TSTG PD TSOLDER 240 245 C/W RJA RJL RJC 75 8.0 1.2 -40 to 125 -40 to 150 -40 to 125 -55 to 150 1.7 C W C Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. ESD data available upon request. 3. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-002), the Machine Model (MM) (AEC-Q100003), and the Charge Device Model (CDM), Robotic (AEC-Q100-011). 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter's approx. average value with VPWR = 13V, TA = 25C. Characteristic POWER INPUT (VDD, VPWR) Supply Voltage(4) Fully Operational Full Parameter Specification Supply Current All Outputs Disabled (Normal Mode) Sleep State Supply Current (Must have VDD 0.8V for sleep state), VPWR = 18V VPWR Over-voltage Shutdown Threshold Voltage(5) VPWR Over-voltage Shutdown Hysteresis Voltage VPWR Under-voltage Shutdown Threshold Voltage (6) Symbol Min Typ Max Unit VPWR (FO) IVPWR (ON) 4.5 9.0 - 36 18 V mA - IVPWR (SS) - VPWR(OV) VPWR(OV-HYS) VPWR(UV) VPWR(UV-HYS) VPWR(LOV) VDD IVDD - VDD(UV) 0.8 36.5 0.5 3.0 100 5.3 3.0 10.0 14.0 A 15 39 1.5 4.0 200 - - 30 42 3.0 4.4 300 8.99 5.5 V V V mV V V mA VPWR Under-voltage Shutdown Hysteresis Voltage VPWR Low Operating Voltage (Low-voltage reported via the SPI)(7) VDD Supply Voltage VDD Supply Current Static Condition and does not include VDD current out of device VDD Supply Under-voltage (Sleep State) Threshold Voltage(8) INJECTOR DRIVER OUTPUTS (OUT 0:3) Drain-to-Source ON Resistance IOUT = 1.0A, TJ = 125C, VPWR = 13V IOUT = 1.0A, TJ = 25C, VPWR = 13V IOUT = 1.0A, TJ = -40C, VPWR = 13V Output Self Limiting Current Output Fault Detection Voltage Threshold(9) - 2.5 1.0 2.8 V RDS (ON) - - - IOUT (LIM) VOUT(FLT-TH) 2.0 I(OFF)OCO 40 I(ON)OCO 20 100 200 75 100 2.5 3.0 3.0 - 0.2 - - 0.3 - - 6.0 A Outputs Programmed OFF (Open Load) Outputs Programmed ON (Short to Battery) Output OFF Open Load Detection Current VDRAIN = 18V, Outputs Programmed OFF Output ON Open Load Detection Current Current less then specification value considered open V A mA Notes 4. These parameters are guaranteed by design, but not production tested. Fully operational means driver outputs will toggle as expected with input toggling. SPI is guaranteed to be operational when VPWR > 4.5V. SPI may not report correctly when VPWR < 4.5V. 5. Over-voltage thresholds minimum and maximum include hysteresis. 6. Under-voltage thresholds minimum and maximum include hysteresis. 7. Device is functional provided TJ is less than 150C. Some table parameters may be out of specification. 8. 9. Device in Sleep State, returns from sleep state with power on reset. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 33810 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter's approx. average value with VPWR = 13V, TA = 25C. Characteristic INJECTOR DRIVER OUTPUTS (OUT 0:3) (Continued) Output Clamp Voltage 1 ID = 20mA Output Leakage Current VDD = 5.0V, VDRAIN = 24V, Open Load Detection Current Disabled VDD = 5.0V, VDRAIN = VOC - 1.0V, Open Load Detection Current Disabled VDD = 0V, VDRAIN = 24V, Sleep State Over-temperature Shutdown(10) Over-temperature Shutdown Hysteresis(10) IGNITION (IGBT) GATE DRIVER PARAMETERS (GD 0:3 FB0:3) Gate Drive Output Voltage IGD = 500A IGD = -500A Sleep Mode Gate to Source Resistor Sleep Mode FBx pin Leakage Current VDD = 0V, VFBx = 24V, Feedback Sense Current (FBx Input Current) FBx = 18V, Outputs Programmed OFF Gate Drive Source Current (1 VGD 3) Gate Drive Turn Off Resistance I GATEDRIVE RDS(ON) 500 SOFT SHUTDOWN FUNCTION (VOLTAGES REFERENCED TO IGBT COLLECTOR) Low Voltage Flyback Clamp Driver Command Off, Soft Shutdown Enabled, GDx = 2.0V Spark Duration Comparator Threshold (referenced to IC Ground Tab) Rising Edge Relative to VPWR Spark Duration Comparator Threshold (referenced to IC Ground Tab)(11) Falling Edge Relative to VPWR, Default = 5.5V Assuming ideal external 10:1 voltage divider. Voltage measured at high end of divider, not at pin. Tolerance of divider not included Open Secondary Comparator Threshold (referenced from primary to Rising Edge Relative to GND. No hysteresis with 10:1 voltage divider. CURRENT SENSE COMPARATOR (RSP, RSN) NOMI Trip Threshold Accuracy - Steady State Condition 3.0A across 0.02 (RSP - RSN = 60mV) 10.75A across 0.04 (RSP - RSN = 430mV) NOMITRIPTA - -4.0 4.0 % VTH-RISE 11.5 - 15.5 VTH-FALL VLVC VTH-RISE 18 2.0 4.9 7.4 9.9 21 2.75 5.5 8.2 11.00 24 3.5 6.1 9.1 12.1 V VPWR +9.0 VPWR +11 VPWR + 13 V V - 1000 685 780 IFBX(FLT-SNS) 1.0 875 A V GS (ON) V GS (OFF) R GS (PULLDOW N) Symbol Min Typ Max Unit VOC1 48 IOUT (LKG) - - - TLIM TLIM (HYS) 155 5.0 - - - - 10 20 3000 10 185 15 53 58 V A C C 5 0 100 7.0 0.375 200 9.0 0.5 300 V K A IFBX (LKG) - - 1.0 A V Notes 10. This parameter is guaranteed by design, however is not production tested. 11. Assuming Ideal external 10:1 Voltage Divider. Tolerance of 10:1 Voltage Divider is not included. Voltage is measured on the High End of Divider - not at the pin. 10:1 N.3.A 10:1 Voltage Divider is produced using two resistors with a 9:1 resistance ratio by the basic formula: VOUT = --------------------R1 ----------------VIN R1 + R2 Where R2 = 9XR1 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter's approx. average value with VPWR = 13V, TA = 25C. Characteristic CURRENT SENSE COMPARATOR (RSP, RSN) (CONTINUED) MAXI Trip Threshold Accuracy Steady State Condition 6.0A across 0.02 (RSP - RSN = 120mV) 21A across 0.04 (RSP - RSN = 840mV) MAXI Trip Point During Overlapping Dwell Input Bias Current RSP and RSN Comparator Hysteresis Voltage NOMI MAXI Input Voltage Range (Maximum voltage between RSN and RSP) Ground Offset Voltage Range Maximum offset between RSN pin and IC Ground (Exposed Pad) GENERAL PURPOSE GATE DRIVER PARAMETERS (GD 0:3) Gate Drive Sink and Source Current Gate Drive Output Voltage IGD = 1mA IGD = -1mA Short to Battery Fault Detection Voltage Threshold VDD = 5.0V, Outputs Programmed ON Programmable from 0.5V to 3.0V in 0.5V increments. (Table 14) Open Fault Detection Voltage Threshold (referenced to IC ground tab) VDD = 5.0V, Outputs Programmed OFF Output OFF Open Load Detection Current FBx = 18V, Outputs Programmed OFF Output Clamp Voltage Driver Command Off, Clamp Enabled, VGATE = 2.0V DIGITAL INTERFACE Input Logic High-voltage Thresholds Input Logic Low-voltage Thresholds Input Logic-voltage Hysteresis Input Logic Capacitance Sleep Mode Input Logic Current VDD = 0V Input Logic Pull-down Current 0.8V to 5.0V (DINX and GINX) Input Logic Pull-down Current 0.8V to 5.0V (SI) Input Logic Pull-up Current on OUT_EN OUT_EN = 0.0V, VDD = 5.0V IOUT_EN_PU -30 -50 -100 ILOGIC_PD ISI_PD 5.0 15 25 A 30 50 100 A VIH VIL VHYS CIN I LOGIC_SS -10 - 10 A 0.7 x VDD GND - 0.3 100 - - - - - VDD + 0.3 0.2 x VDD 300 20 V V mV pF A VOC 48 53 58 IFBX(FLT-SNS) 40 75 100 V VDS(FLT-TH) 2.0 2.5 3.0 A V GS (ON) V GS (OFF) VDS(FLT-TH) -20% +20% V 5.0 0.0 7.0 0.2 9.0 0.5 V V V IGD 1.0 2.0 5 mA NOMIHYS MAXIIHYS VCMVRCMVR VGNDOVR 40 40 0.0 -0.3 - - - - 60 60 2.0 0.3 V V % of VT MAXITRIPTA -7.5 MAXITRIPOD IBIASRSX -50 -15 - - +15 50 % A - 7.5 % Symbol Min Typ Max Unit 33810 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter's approx. average value with VPWR = 13V, TA = 25C. Characteristic DIGITAL INTERFACE (CONTINUED) OUT_EN Leakage Current to VDD OUT_EN = 5.0V, VDD = 0V SCLK Pull-down Current VSCLK = VDD Tri-state SO Output 0V to 5.0V CS Input Current CS = VDD CS Pull-up Current CS = 0V CS Leakage Current to VDD CS = 5.0V, VDD = 0V SO Input Capacitance in Tri-state Mode SO High State Output Voltage ISO-HIGH = -1.0mA SO Low State Output Voltage ISO-LOW = 1.0mA NOMI, MAXI in V10 Mode Pull-down Current NOMI, MAXI = 0.8V, VDD = 5.0V SPKDUR Output Voltage ISPKDUR = 1.0mA Output Pull-up Current for SPKDUR NOMI, MAXI High State Output Voltage INOMI-HIGH = -1.0mA IMAXI-HIGH = -1.0mA NOMI, MAXI Low State Output Voltage INOMI-LOW = 250A IMAXI-LOW = 250A VI_LOW - - 0.4 ISPKDUR_PV VI_HIGH VDD - 0.4 - - VSPKDUR_LO - 30 - 50 0.4 100 A V IPD 30 70 100 V VSO_LOW - - 0.4 A CSO VSO_HIGH VDD - 0.4 - - V ICS(LKG) - - - 20 50 - pF V ICS_PU -30 -50 -100 A ICS -10 - 10 A I TRISO -10 - 10 A I SCLK 5 15 25 A IOUT_EN(LKG) - - 50 A A Symbol Min Typ Max Unit V 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13V, TA = 25C. Characteristic POWER INPUT Required Low State Duration on VPWR for Under-voltage Detect VPWR 0.2V Required Low State Duration on VDD for Power On Reset VDD 0.2V INJECTOR DRIVERS Output ON Current Limit Fault Filter Timer (Short to Battery Fault) Output ON Open Circuit Fault Filter Timer Output Retry Timer Output OFF Open Circuit Fault Filter Timer Output Slew Rate (No faster than 1.5s from off to on and on to off) RLOAD = 14, VLOAD = 14V Output Slew Rate RLOAD = 14, VLOAD = 14V Propagation Delay (Input Rising Edge OR CS to Output Falling Edge) Input @ 50%VDD to Output voltage 90% of VLOAD Propagation Delay (Input Falling Edge OR CS to Output Rising Edge) Input @ 50%VDD to Output voltage 10% of VLOAD IGNITION & GENERAL PURPOSE GATE DRIVER PARAMETERS Propagation Delay (GINx Input Rising Edge OR CS to Output Rising Edge) Input @ 50%VDD to Output voltage 10% of V GS (ON) Propagation Delay (Input Falling Edge OR CS to Output Falling Edge) Input @ 50%VDD to Output voltage 90% of V GS (ON) IGNITION PARAMETERS Open Secondary Fault Timer accuracy (uncalibrated) Maximum Dwell Timer Accuracy (uncalibrated) End of Spark Filter Accuracy (uncalibrated) (12) Symbol Min Typ Max Unit tUV 1.0 t RESET 1.0 - - - - s s tSC t(ON)OC tREF t(OFF)OC 30 3.0 - 100 60 7.5 10 90 12 15 400 s ms ms s V/s t SR(RISE) 1.0 5.0 10 t SR(FALL) 1.0 tPHL 5.0 1.0 10 5.0 V/s s tPLH 1.0 5.0 s tPLH 0.2 1.0 s tPHL 0.2 1.0 s -35 -35 -35 - - - 35 35 35 % % % Notes 12. This parameter is guaranteed by design, however it is not production tested. 33810 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions of 3.0V VDD 5.5V, 9.0V VPWR 18V, -40C TC 125C, and calibrated timers, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13V, TA = 25C. Characteristic GENERAL PURPOSE GATE DRIVER PARAMETERS Short to Battery Fault Detection Filter Timer Accuracy VDD = High, Outputs Programmed ON Programmable from 30s to 960s in replicating increments Tolerance of timer after using calibration command Tolerance of timer before using calibration command Output OFF Open Circuit Fault Filter Timer VDD = 5.0V, Outputs Off Tolerance of timer before using calibration command PWM Frequency 10Hz to 1.28kHz Tolerance after using calibration command PWM Frequency 10Hz to 1.28kHz Tolerance before using calibration command Gate Driver Short Fault Duty Cycle SPI DIGITAL INTERFACE TIMING(13) t LEAD 100 t LAG 50 t SI (SU) 16 t SI (HOLD) 20 t R (SI) t F (SI) (16) (17) Symbol Min Typ Max Unit VDS(flt-th) % -10 -35 t(OFF)OC 100 PWMFREQ PWMFREQ GDSHRT_DC -10% -35% 1.0 +10 +35 s 400 10% 35% 3.0 % Falling Edge of CS to Rising Edge of SCLK Required Setup Time Falling Edge of SCLK to Rising Edge of CS Required Setup Time SI to Rising Edge of SCLK Required Setup Time Rising Edge of SCLK to SI Required Hold Time SI, CS, SCLK Signal Rise Time(14) SI, CS, SCLK Signal Fall Time(15) ns - - ns - - ns - - ns - 5.0 5.0 - - 25 - - - - 55 55 55 - ns ns ns ns ns s - - - - - 1.0 Time from Falling Edge of CS Low-impedance t SO (EN) t SO (DIS) t VALID tSTR (18) Time from Rising Edge off CS to SO High-impedance Time from Falling Edge of SCLK to SO Data Valid Sequential Transfer Rate Time required between data transfers DIGITAL INTERFACE Calibrated Timer Accuracy Un-calibrated Timer Accuracy Notes 13. 14. 15. 16. 17. 18. t TIMER t TIMER - - - - 10 35 % % These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface. This parameter is guaranteed by design, however it is not production tested. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS 0.2 VDD tLEAD 0.7 VDD 0.2 VDD tSI(SU) tSI(HOLD) tLAG SCLK SI 0.7 VDD 0.2 VDD MSB IN tSO(EN) SO 0.7 VDD 0.2 VDD MSB OUT tVALID LSB OUT tSO(DIS) 33810 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ANALOG SUPPLY VOLTAGE (VPWR) The VPWR pin is the battery input to the 33810 IC. The VPWR pin requires external reverse battery and transient protection. All IC analog current and internal logic current is provided from the VPWR pin. With VDD applied to the IC, the application of VPWR will perform a POR. SERIAL INPUT DATA (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 16 bits of information or multiples of 8 there of must be entered into the device. DIGITAL LOGIC SUPPLY VOLTAGE (VDD) The VDD input pin is used to determine communication logic levels between the microprocessor and the 33810 IC. Current from VDD is used to drive SO output and the pull-up current for CS. VDD must be applied for normal mode operation. Removing VDD from the IC will place the device in sleep mode. With VPWR applied to the IC, the application of VDD will perform a POR. SERIAL OUTPUT DATA (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CS enables the SO driver. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. GROUND (GND) The bottom pad or FLAG provides the only ground connection for the IC. The VPWR and VDD supplies are both referenced to the GND pad. The GND pad is used for both de-coupling the power supplies as well as power ground for the output drivers. Although the silicon die is epoxy attached to the top side of the pad, the pad must be grounded for proper electrical operation. OUTPUT ENABLE (OUTEN) The OUTEN pin is an active low input. When the OUTEN pin is low, all the device outputs are active. The outputs are all disabled when OUTEN pin is high. SPI and parallel communications are still active in either state of OUTEN. SERIAL CLOCK INPUT (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33810. The SI data is latched into the input shift register on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read on the rising edge of SCLK. With CS in a logic high state, signals on the SCLK and SI pins will be ignored and the SO pin is tri-state FEEDBACK VOLTAGE SENSOR (FB0-FB3) The FBx pin has multiple functions for control and diagnostics of the external MOSFET/IGBT Ignition gate driver. In Ignition (IGBT) Gate Driver Mode, the feedback inputs monitor the IGBT's collector voltage to provide the spark duration timer control signal. The spark duration timer monitors this input to determine if the secondary clamp function should be activated. In secondary clamp mode, the IGBT's collector voltage is internally clamped to VPWR+11V. In the General Purpose Gate Driver mode, this input monitors the drain of an external MOSFET to provide shortcircuit and open circuit detection by monitoring the MOSFET's drain to source voltage. The filter timer and threshold voltage are easily programmed through SPI (See tables 18 and 19 for SPI messages). In General Purpose Gate Driver mode the FBx pin also provides a drain to gate clamp for fast turn off of inductive loads and external MOSFET protection. CHIP SELECT (CS) The system MCU selects the 33810 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command words may be sent to the 33810 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output and transfers status information into the SO buffer. Rising edge of the CS initiates the following operation: Disables the SO driver (high-impedance) Activates the received command word, allowing the 33810 to activate/deactivate output drivers. To avoid any spurious data, it is essential that the high-tolow and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33810 device is an active pull-up to VDD on CS. GATE DRIVER OUTPUT (GD0-GD3) The GDX pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to hold the external device in the OFF state while the device is in the POR or SLEEP state. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION LOW SIDE INJECTOR DRIVER OUTPUT (OUT0 OUT3) OUT0 - OUT3 are the Open drain low side (Injector) driver outputs. The drain voltage is actively clamped during turn off of inductive loads. These outputs can be connected in parallel for higher current loads provided the turn off energy rating is not exceeded. SPARK DURATION OUTPUT (SPKDUR) SPKDUR is the Spark Duration output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed spark detection threshold. This output indicates an ignition flyback event. Each feedback input (FB0 - FB3) is logically OR'd to drive the SPKDUR output. There is a 50A pull up current source connected internally to the SPKDUR pin. RESISTOR SENSE POSITIVE (RSP) Resistor Sense Positive - Positive input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected between RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. MAXIMUM IGNITION COIL CURRENT (MAXI) Maximum ignition coil current output flag. This output is asserted when the output ignition coil current exceeds the selected level of the DAC. This signal also latches off the gate drive outputs when configured as an ignition gate driver. The MAXI current level is determined by the voltage drop across an external sense resistor connected to pins RSP and RSN. MAXI can be configured as an input pin for V10 applications where the gate drive needs to be latched off by another devices MAXI current sense amplifier output. The MAXI input will latch off gate drivers 7 and 8 when configured as ignition gate drive outputs See Figure 10. RESISTOR SENSE NEGATIVE (RSN) Resistor Sense Negative - Negative input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected to RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. DRIVER INPUT (DIN0-DIN3), GATE DRIVER INPUT (GIN0-GIN3) Parallel input pins for OUT0-OUT3 low side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an internal pull-down current sink. The parallel input data is logically OR'd with the corresponding SPI input data register contents, except for the ignition mode IGBT drivers. They are only controlled by the parallel inputs GIN0-GIN3. In GPGD mode, GIN0-GIN3 are logically OR'd with SPI input data. All outputs are disabled when the OUTEN pin is HIGH, regardless of the state of the command inputs. NOMINAL IGNITION COIL CURRENT (NOMI) Nominal ignition coil current output flag. This output is asserted when the output current exceeds the level selected by the DAC. NOMI can be configured as an input pin for V10 mode applications where the gate drive needs to be latched off by another device's MAXI current sense amplifier output. The NOMI input will latch off gate drivers 5 and 6 when configured as a V10 mode ignition gate driver See Figure 10. 33810 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Figure 4. Functional Internal Block Diagram POWER SUPPLY/POR The 33810 is designed to operate from 4.5V to 36V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog, and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC architecture provides a low quiescent current sleep mode. Applying VPWR and VDD to the device will generate a Power On Reset (POR) and place the device in the Normal State. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing a POR. with the corresponding SPI input data register contents. All outputs are disabled when the OUTEN pin is HIGH, regardless of the state of the command inputs. INJECTOR DRIVERS: OUT0 - OUT3 These pins are the Open drain low side (Injector) driver outputs. The drain voltage is actively clamped during turn off of inductive loads. These outputs can be connected in parallel for higher current loads, provided the turn off energy rating is not exceeded. IGNITION GATE PRE-DRIVERS: GD0 - GD3 MCU INTERFACE AND OUTPUT CONTROL This component provides parallel input pins for OUT0OUT3 low side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an internal pulldown current sink. The parallel input data is logically OR'd These pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to hold the external device in the OFF state while the device is in the POR or Sleep State. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER SUPPLY The 33810 is designed to operate from 4.5V to 36V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC architecture provides flexible microprocessor interfacing and low quiescent current sleep mode. Control register settings from a Power-ON Reset (POR) are as follows: * All outputs off * IGNITION gate driver mode enabled (IGBT Ignition Mode). * PWM frequency and duty cycle control disabled. * Off State open load detection enabled (LSD) * MAXI dac set to 14A, NOMI DAC set to 5.5A * Spark detect level VIL DAC set to VPWR +5.5V * Open secondary timer set to 100s * Dwell timer set 32ms * Soft shutdown disabled * Low-voltage flyback clamp disabled * Dwell overlap MAXI offset disabled POWER-ON RESET (POR) Applying VPWR and VDD to the device will generate a Power On Reset (POR) and place the device in the Normal State. The Power On Reset circuit incorporates a filter to prevent high frequency transients from causing a POR. All outputs are disabled when the OUTEN input pin is HIGH regardless of the SPI control registers or the logic level on the parallel input pins. With the OUTEN pin high, SPI messages may be sent and received by the device. Upon enabling the device (OUTEN low), outputs will be activated based on the state of the command register or parallel input. Table 5. Operational States VPWR L L H H VDD L H L OUTEN X X X X OUTPUTS OFF OFF OFF OFF STATE Power Off POR SLEEP POR MODES OF OPERATION In Normal State, the 33810 gate driver has three modes of operation, ignition Mode, GPGD (General Purpose Gate Driver) Mode and V10 mode.The operating mode of each gate driver may be set individually and is programmed using the Mode Select Command. MODE SELECT COMMAND The MODE Select Command is used to set the operating mode for the GDx gate driver outputs, over/under-voltage operation and to enable V10 Mode and the PWM generators. The Mode Select Command programmable features are listed below. * Ignition/GPGD Mode select (gate drivers) * V10 Mode enable * Over/Under-voltage operation for all drivers * GPGD PWM controller enable H X OFF POR IGNITION/GPGD MODE SELECT L X OFF SLEEP H H H H L H ACTIVE OFF NORMAL NORMAL SLEEP STATE Sleep State is entered when the VDD supply voltage is removed from the VDD pin. In Sleep State all outputs are off. Applying VDD will force the device to exit the Sleep State and generates a POR. The Ignition/General Purpose Gate Driver Mode select bits determine independently, the operating mode of each of the GDx gate driver outputs. Bits 8,9,10,11 correspond to GD0, GD1, GD2, GD3 respectively. Setting the bit to a logic 0 sets the GDx driver to the Ignition Mode. Setting the bit to a logic 1 commands the GDX driver to the General Purpose Mode and disables the ignition features for that particular gate driver (except the MAXI current shutdown feature). Further information on GDx gate driver in Ignition Mode and General Purpose Mode is provided later in this section of the data sheet. V10 MODE ENABLE BIT The V10 Enable bit allows the user to configure the device for 10 cylinder applications. When the V10 Mode is enabled, the device configures the NOMI pin and MAXI pin as digital inputs rather than outputs. The new MAXI input pin receives NORMAL STATE The default Normal State is entered when power is applied to the VPWR and VDD pins. 33810 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES the MAXI shutdown signal for GD0 and GD2 and the new NOMI input pin receives the MAXI shutdown signal for GD1 and GD3. Further information on V10 Mode is provided in the V10 Application section. Note: RSN and RSP must be grounded in V10 Mode. IGNITION (IGBT) GATE DRIVER MODE The MC33810 contains dedicated circuitry necessary for automotive ignition control systems. Each gate driver may be individually configured as an Ignition Gate Driver with the following features: Spark duration signal Open secondary timer Soft shutdown control Low-voltage flyback clamp Ignition ignition coil current measurement MAXI output and control NOMI output Maximum dwell timer In the Ignition Mode, several control strategies are in place to control the IGBT for enhanced system performance. Information acquired from the FBx pin allows the device to produce a spark duration signal output (SPKDUR) and detect open secondary ignition coils. Based on the FBx signal and Spark Command register settings, the device performs the appropriate gate control (Low-voltage Flyback Clamp, Soft Shutdown) and produces the SPKDUR output. The FBx pin is connected to the collector of the IGBT through an external 9:1 resistor divider network. The recommended values for the resistor divider network is 36K and 4.02K, with the 36K resistor connected from the IGBT collector to the FBx pin and the 4.02K resistor connected from the FBx pin to ground. Additional controls to the gate driver are achieved by sensing the current through the external IGBT. The Resistor Sense Positive (RSP) and Resistor Sense Negative (RSN) inputs are use to measure the voltage across an external 20m or 40m current sense resistor. A gain select bit in the Spark Command SPI Command messages should be set to 1 (gain of 2) when using a 20m current sense resistor. When using a 40m current sense resistor, the gain select bit should be set to 0 (gain of 1 is the default value). The ignition coil current is compared with the output of the DACs which have been programmed via the SPI Commands. The comparison generates the Nominal Current signal (NOMI) and the Maximum Current signal (MAXI). Both signals have a low output when the ignition coil current is below the programmed DAC value and a high output when the current is above the programmed DAC value. When the GDx output is shutdown because of the control strategy, the output may be activated again by toggling the input control. * * * * * * * * OVER/UNDER-VOLTAGE SHUTDOWN/RETRY BIT The Over/Under-voltage Shutdown/Retry bit allows the user to select the global over and under-voltage fault strategy for all the outputs. In an over-voltage or under-voltage condition on the VPWR pin, all outputs are commanded off. The Over/Under-voltage control bit sets the operation of the outputs when returning from over/under- voltage. Setting the Over/Under-voltage bit to logic [1] will force all outputs to remain OFF when VPWR returns to normal level. To turn the output on again, the corresponding input pin or SPI bit must be reactivated. Setting the Over/Under-voltage bit to logic [0] will command all outputs to resume their previous state when VPWR returns to normal level. Table 6 below provides the output state when returning from over or under-voltage. Table 6. Over-voltage/Under-voltage Truth Table GINx DINx Input Pin SPI Bit Over/ Undervoltage Control Bit X 1 0* 0* 0* OUTEN Input pin State When Returning From Over/Under-voltage OFF OFF OFF ON ON X X 0 X 1 X X 0 1 X 1 0 0 0 0 * Default Setting Note: The SPI bit does not control the Gate Driver outputs in the Ignition Mode, only in the GPGD Mode. An under-voltage condition on VDD results in the global shutdown of all outputs and reset of all internal control registers. The VDD under-voltage threshold is between 0.8V and 2.8V PWMX ENABLE BIT Gate Driver outputs programmed as General Purpose Gate Drivers may be used as low frequency PWM outputs. The PWM generators are enabled via bits 0 through 3 in the Mode Select Command. Bits 0 through 3 correspond to outputs GD0 through GD3 respectively. Once the frequency and duty cycle are programmed through the PWM Frequency & DC command, the PWM output may be turned ON and OFF through the PWM enable bit. Further information on PWM control is provided in the General Purpose Gate Driver Mode section of this data sheet. SPARK COMMAND The Spark Command is an ignition mode command used to program the parameters for the ignition mode features listed below: * End spark threshold (EndSparkTh bits) * Open secondary fault timer (OSFLT bits) 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES * * * * * * * Secondary clamp (secondary clamp bit) Soft shutdown enable (SoftShutDn bit) Ignition ignition coil current amplifier gain (Gain Sel bit) Overlapping dwell disable (Overlap Dwell Disable bit) Maximum dwell enable (MaxDwellEn bit) Maximum dwell timer (MaxDwellTimer bits) End of spark filter timer value Spark Command address and data bits are listed in Table 20 NOTE: Gate driver outputs programmed to be General Purpose Gate Drivers are not affected by the Spark Commands. VPWR = 16.0V Default settings Begin spark threshold VIH = VPWR + 21V End spark threshold VIL = VPWR +5.5V The pulse width of the SPKDUR signal is measured by the MCU timer/input capture port to determine the actual spark duration. Spark duration information is then used by the MCU spark control algorithm to optimize the dwell time. Table 7. End Spark Threshold Spark Command Bit SPARK DURATION SIGNAL The Spark Duration is defined as the beginning of current flow to the end of current flow across the spark plug gap. Because the extremely high-voltage ignition coil secondary output is difficult to monitor, corresponding lower voltage signals generated on the ignition coil primary are often used. The FBx pins monitor the ignition coil primary voltage (IGBT Collector) through a 10 to 1 voltage divider. When the IGBT is disabled, the rise in the FBx signal indicates a sparkout condition is occurring at the spark plug gap. The device considers the initial thresholds for spark duration to be VIH = VPWR + 21V for rising edge as measured on the collector of the IGBT. The spark duration falling edge reference is programmable via SPI through the End Spark Threshold bits 0 and 1 (See Table 7). Figure 5 illustrates a typical ignition event with dwell time and spark duration indicated. Figure 5. Ignition Coil Charge and Spark Event OPEN SECONDARY TIMER A fault due to open in the ignition coil secondary circuit can be determined by waveforms established on the ignition coil primary during a spark event. The spark event is initiated by the turn off of the IGBT. The voltage on the collector of the IGBT rises up to the IGBT's internal collector to gate clamp voltage (typically 400 volts). Collector to gate clamp events normally last 5s to 50s. In an open ignition coil secondary fault condition, the collector to gate clamp event lasts much longer. The oscilloscope waveform in Figure 6 and Figure 7 compare a normal spark signature with that of an open secondary fault condition signature. Figure 6. Normal Spark Event Ignition Coil Current, 5.0A/div DWELL Time SPKDUR~3.0ms Channel 1: GINx IGBT Gate Drive Channel 2: IGBT Collector Voltage Channel 3: IGBT Current @ 5.0A/Div 33810 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Figure 7. Open Secondary Spark Event The Low-voltage Clamp spreads out the energy dissipation over a longer period of time, thus allowing the use of a lower energy rated IGBTs. The internal low-voltage clamp is connected between the IGBT's collector (through an external resistor) and the IGBT's gate. The energy stored in the ignition coil is dissipated by the IGBT, not the internal clamp. The internal clamp only provides the bias to the IGBT. Several logical signals are required as inputs to activate the GDx Low-voltage Clamp feature. The GDx Low-voltage Clamp feature may be disabled through bit 4 of the Spark Command message. Figure 8. Low-voltage Clamp + - + - SPI SPARK DURATION Open Secondary SPI 100A VPWR + - FB0 FB1 FB2 FB3 13V 53V The Open Secondary timer is initiated on the rising edge of the ignition coil primary spark signal and terminated on the falling edge. The rising edge Open Secondary Threshold is VIH= 135V at primary, no hysteresis. The falling edge Open Secondary threshold is VIL = 135V. Collector to gate clamp durations that last longer than the selected Open Secondary Fault Time interval (Table 8) indicates a failed spark event. When the Open Secondary Fault Time is exceeded and the Low-voltage Clamp is enabled, the GDx output will activate the Low-voltage Clamp shown in figure 16. The Logic for this Low-voltage Clamp is defined in Figure 9 Table 8. Open Secondary Timer Spark Command Bits SPI input GATE DRIVE CONTROL Low V Clamp GPGD Clamp GD0 GD1 GD2 GD3 Figure 9. Low-voltage Clamp Logic OSFLT_En IGN Mode OSFLT MaxDwell MaxDwellEn SoftShutDnEn IGN Mode VPWR OVER-VOLTAGE OUTEN Activate Low-voltage Clamp LOW-VOLTAGE CLAMP The Low-voltage Clamp is an internal clamp circuit which biases the IGBT's gate voltage in order to control the collector to emitter voltage to VPWR+11V. This technique is used to dissipate the energy stored in the ignition coil over a longer period of time than if the internal IGBT clamp were used. In the open secondary fault condition, all of the stored energy in the ignition coil is dissipated by the IGBT. This fault condition requires the use of a higher energy rated IGBT than would otherwise be needed. SOFT SHUTDOWN ENABLE The soft shutdown feature is enabled via the SPI by asserting control bit 5 in the Spark Command message. When enabled, the following events initiate a soft shutdown control of the gate driver. * OUTEN = High (Outputs Disabled) * Over-voltage on VPWR pin 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES * Max dwell time Soft Shutdown is designed to prevent an ignition spark while turning off the external IGBT. The Low-voltage Clamp is activated to provide the mechanism for a soft shutdown. The Max Dwell gate turn off signal is a logically ANDed with the Soft Shutdown bit to activate a Low-voltage Active Clamp (See Figure 9). Table 10. Maximum Dwell Timer GAIN SELECT BIT The ignition coil current comparators are used to compare the programmed NOMI and MAXI DAC value with voltage across the external current sense resistor. When selecting a gain of two, the ignition coil current sense resistor must be reduced from 40m to 20m. Spark Command Bit MAX Dwell Timer MaxDwell (ms) 2 4 8 16 32 (default) 64 64 64 OVERLAPPING DWELL ENABLE BIT Overlapping dwell occurs when two or more ignition mode drivers are commanded ON at the same time. In this condition, with the Overlapping Dwell Bit enabled the MAXI DAC threshold value is increased as a percentage of the nominal programmed value. The percent increase is determined by bit 5 through bit 7 of the DAC Command. Table 9. Overlapping Dwell Compensation DAC Command Bits 100 101 110 111 DAC COMMAND (DIGITAL TO ANALOG CONVERSION COMMAND) The DAC Command is an ignition mode command that sets the nominal ignition coil current (NOMI) and maximum ignition coil current (MAXI) DAC values. Bits 0 through 4 set the NOMI threshold value and, bits 8 through 11 set the MAXI threshold values. The DAC command and default values are listed in the SPI Command Summary Table 20. The NOMI output is used by the MCU as a variable in dwell and spark control algorithms. NOMI DAC BITS The NOMI output signal is generated by comparing the external current sense resistor differential voltage (Resistor Sense Positive, Resistor Sense Negative) with the SPI programmed NOMI DAC value. When the NOMI event occurs, the NOMI output pin is asserted (High). The NOMI output is only a flag to the MCU and it's output does not affect the gate driver. When using a 20 m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 2, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =1. When using a 40m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 1, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =0. This is also the default value. The NOMI output provides a means to alert the MCU when the ignition coil primary current equals the value programmed into the NOMI DAC. In V10 Mode, the NOMI pin is reconfigured as a MAXI input pin from a third MC33810 device in the system. In this mode a NOMI input has effectively the same control as an internal MAXI signal. Further information is provided in the V10 Mode application section of this data sheet. MAXIMUM DWELL ENABLE BIT Bit 8, the Maximum Dwell Enable bit allows the user to enable the Maximum Dwell Gate Turnoff Feature. When the Max Dwell bit is programmed as logic 0 (disabled) the device will not perform a Low-voltage Clamp due to Max Dwell (See Figure 9). MAXIMUM DWELL GATE TURN OFF FEATURE In automotive ignition systems, dwell time is defined as the duration of time that an ignition coil is allowed to charge. The MC33810 starts the measure of time from the gate drive ON command. If the dwell time is greater than the Max Dwell Timer setting (Table 10), the offending ignition gate driver is commanded OFF. The Max Dwell Gate Turn Off Feature may be disabled via bit 8 of the Spark Command. When the feature is disabled, the Max Dwell fault bits are always logic 0. The Max Dwell Timer feature pertains to Ignition Mode only and does not affect gate drivers configured as general purpose gate drivers. 33810 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 11. Nominal Current DAC Select Differential Voltage (mV Rs = 20m (Gain = 2) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 Differential Voltage (mV Rs = 40m (Gain = 1) 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 Table 11. Nominal Current DAC Select Differential Voltage (mV Rs = 20m (Gain = 2) 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 160 165 170 175 180 185 190 195 200 205 210 215 Differential Voltage (mV Rs = 40m (Gain = 1) 320 330 340 350 360 370 380 390 400 410 420 430 DAC Command Bits<4,3,2,1,0> NOMI Current (A) DAC Command Bits<4,3,2,1,0> NOMI Current (A) MAXI DAC BITS The MAXI control block provides a means to shut off all the ignition coil drivers if the current reaches a SPI programmable maximum level. Control is achieved by comparing the output of the current sense amplifier with a SPI programmed DAC value. The MAXI comparator disables all gate drivers configured as ignition drivers when the DAC MAXI setting is exceeded. When a MAXI event occurs, the MAXI bit in the fault status register is set and the MAXI pin is asserted (High). When using a 20m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 2, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =1. When using a 40m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 1, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =0. This is also the default value. The MAXI fault bit in the SPI fault status register is cleared when the MAXI condition no longer exists and the SPI fault status register has been read by the MCU. In V10 Mode, the MAXI pin is configured as an input to receive the MAXI signal from a second MC33810 device in the system. In this mode a input MAXI signal has effectively the same control as an internal MAXI signal. Further information is provided in the V10 Mode application section of this specification. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES GENERAL PURPOSE GATE DRIVER MODE Table 12. Maximum Current DAC Select DAC Command Bit Each gate driver can be individually configured as a General Purpose Gate Driver (GPGD) and controlled from the parallel GINx input pins, SPI Driver ON/OFF Command or may be programmed through the SPI for a specific frequency and duty cycle output (PWM). In General Purpose Gate Driver mode the gate drivers have the following features: * * * * Gate driver for discrete external MOSFET Off state open load detect On state short circuit protection Programmable drain threshold and duration timer for short fault detection * PWM frequency/duty cycle controller In GPGD Mode the GDx output is a current controlled output driver with slew rate control, gate to source clamp, passive pull-down resistor and a drain to gate clamp for switching inductive loads. Driver ON /OFF Command 640 680 720 760 800 840 END OF SPARK FILTER BITS The ringing at the end of the Spark signatures waveform can cause erroneous detection of the End of Spark event. To eliminate the effect of this ringing, a low pass filter with variable time values can be selected. Four time values for the low pass filter have been provided with a zero value indicating that no low pass filtering is to be used. The End of Spark Filter bits specify a 0, 4s, 16s, or 32s time interval to sample the spark ignition coil primary current to ignore the ringing at the end of spark. Table 13. End of Spark Filter Time Select End of Spark Filter Bits<11, 10, 9, 8> 0000 0001 0010 0011 Filter Time s 0.0 4.0 16.0 32.0 The Driver ON/OFF Command, bits 4 through 7 control gate drivers that have been Mode Select Command programmed as GPGD. A logic 1 in bits 4 through 7 will command the specific output ON. A logic 0 in the appropriate bit location commands the specific output Off. Also contained in the Driver ON/OFF Command are SPI control bits for the integrated LSD output drivers. Further information on LSD control is provided in the Low Side Injector Driver section of the data sheet. NOTE: Gate drivers programmed to IGNITION mode have parallel input control only, and cannot be turned off and on via SPI commands. GPGD Short Threshold Voltage Command Each GPGD driver is capable of detecting an open load in the off state and shorted load in the on state. All faults are reported through the SPI communication. For open load detection, a current source is placed between the FBx pin and ground of the IC. An open load fault is reported when the FBx voltage is less than the 2.5V threshold. Open load fault detect threshold is set internally to 2.5V and may not be programmed. A shorted load fault is reported when the FBx pin voltage is greater than the programmed short threshold voltage. The short to battery fault threshold voltage of the external MOSFET is programmed via the GPGD Short Threshold Voltage Command. Table 14 illustrates the bit pattern to select a particular threshold. Drain voltages less than the selected threshold are considered normal operation. Drain voltages greater than the selected threshold voltage are considered faulted. 33810 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 14. FBx Fault Threshold Select GPGD VDS FLT Bits 000 001 010 011 100 101 110 111 FBx Fault Threshold Select 0.5V 1.0V 1.5V 2.0 (default) 2.5V 3.0V No Change No Change GPGD SHORT TIMER COMMAND The GPGD Short Timer Command allows the user to select the duration of time that the drain voltage is allowed to be greater than the programed threshold voltage without causing shutdown. External MOSFETS with drain voltages greater than the programed threshold for longer than the Fault Duration Timer are shutdown. Timer durations are listed in Table 15. Table 15. FBx Short Fault Timer GPGD FLT Timer Bits 000 001 010 011 100 101 110 111 Fault Timer Select 30s 60s 120s 240s (default) 480s 960s No Change No Change Each gate driver is individually set to either, restore to the pre-fault state, or shutdown when a short fault is declared. By setting the Retry/Shutdown bit in the GPGD Fault Operation Command to logic 1 the specific output will try to go back to the pre-fault state when the fault is no longer declared, after a programmed "inhibit time". The retry strategy will cause the output to try to return to the pre-fault state on a 1% duty cycle basis. For example: If the fault timer is set to 120s and a fault is declared (drain voltage greater than the programmed threshold for greater than 120s), the GDx output driver will be forced off for 12ms. After 12 ms has elapsed, if the inputs, GINx or SPI, have not tried to shut off the particular GDx output in the interim, the GDx output will try to set the external driver on again (the prefault state). A continued declared fault on the output would result in another 12ms shutdown period. By setting the Retry/Shutdown bit in the GPGD Fault Operation Command to logic 0 the specific output will shutdown and remain off when the short fault is declared. Only a reissue of the turn on command, via SPI or GINx, will force the output to try and turn on again. In the event that a GPGD is selected as a PWM controller and a short occurs on the output, the output retry strategy forces the output to a 1% duty cycle based on the fault timer setting. For example: If the fault timer is set to 120s and a fault is detected (drain voltage greater than programmed threshold), the PWM output will be commanded off for 12ms and commanded ON again at the next PWM cycle. Care should be taken to select a fault timer that is shorter than the minimum duty cycle ON time of the PWM controller. Selecting a fault timer that is longer will allow the PWM controller to continue to drive the external MOSFET into a shorted load. PWM FREQUENCY/DUTY CYCLE COMMAND The PWMx Freq & Duty Cycle command is use to program the GDx outputs with a frequency and duty cycle. Table 16 defines the user selectable output frequency. The frequency and duty cycle may be updated at any time using the PWM Freq&DC command, however the update will only begin on the next PWM rising edge time. Once the PWM Freq & DC registers are programmed and the PWM controller is enabled through the Mode Command the PWM outputs are turned ON and OFF via the GINx pin OR the SPI GPGD ON/OFF Command control bit. All Parallel and serial On and Off command updates to the PWM controller are synchronous with the rising edge of the previous PWM period. The truth table for GDx control in general purpose mode is provided in Table 8. The duty cycle of the PWM outputs is controlled by bits 06, inclusive. The duty cycle value is 1% per binary count from 1-100 with counts of 101-127 defaulting to 100%. For example, sending SPI command 101001000001100 would set GD1, PWM output to 10Hz and 12% duty cycle. Notes: Tolerance on this fault timer setting is 10% after using the Calibration Command. GPGD FAULT OPERATION COMMAND The GPGD Fault Operation Command sets the operating parameters for the gate drivers under faulted conditions. A short fault is said to be "detected" when the drain source voltage, Vds, of the external MOSFET, exceeds the SPI programmed short threshold voltage. The short fault is said to be "declared" when the VDS over-voltage lasts longer than the SPI programmed "fault timer." (short duration time > fault timer programmed value) 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES . Table 16. Frequency Select PWM Freq&DC Command Bit V10 MODE V10 Mode provides a method for monitoring 10 ignition events while using only two current sense resistors. This is achieved using three MC33810 devices. Two MC33810 devices are programmed as Normal Ignition mode outputs and one is programmed as a V10 ignition mode output. The ignition gate driver outputs are partitioned into two banks of five outputs each (See Figure 10). Each bank contains one or two driver(s) from the V10 device. Drivers in the V10 device are grouped in two's (GD0&GD2, GD1&GD3). Current from each V10 mode IGBT group is monitored by the appropriate Normal Mode device (See Figure 10). The MAXI signal from one Normal Mode device is ported to the V10 Mode MAXI input pin. Likewise the MAXI signal from the second Normal Mode device is ported to the V10 Mode NOMI input pin. The V10 Mode NOMI/MAXI inputs are used as MAXI shutdown signals for the appropriate ignition gate drive group. V10 Mode contains the same features as Ignition Mode gate drivers with the following exceptions: * NOMI/MAXI configured as input pins * MAXI shutdown for GPGD disabled * NOMI/MAXI comparators disabled In V10 Mode, Spark Command bits 7 and 8 (Gain Select, Overlapping Dwell) are disabled. These two features are achieved through the Normal Mode devices. RSN and RSP must be grounded in V10 Mode. Notes: Tolerance on selected frequency is 10% after using the Calibration Command. Shorts to battery and open load faults will not be detected for frequency and duty cycle combinations inconsistent with fault timers. Table 17. Pre-driver GDx Output Control Mode Command IGN/GP Bit 1 1 1 1 1 Driver On/OFF GPGD Bit 0 0 1 X 1 PWMx Enable Bit X 0 0 1 1 GINx terminal 0 1 X 1 X GDx Output OFF ON ON Freq/DC Freq/DC 33810 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Bank 1 IC 1 "Parent" GIN0 Gate Drive 0 GIN1 Gate Drive 1 GIN2 Gate Drive 2 GIN3 Gate Drive 3 4 GIN (0-3) NOMI LOGIC MAXI RSP1 RS1 Ign 1 RSP Child Comparator Inputs Tied to GND VtNI Bank 2 IC 2 "Parent" GIN0 Gate Drive 0 GO1 IGBT26 GO1 IGBT 2 (0-3) GO2 GO3 IGBT27 4 GIN1 GIN2 GIN3 GIN (0-3) NOMI MAXI GO0 GIN0 IC 3 "Child" IGBT14 GO0 GO0 IGBT1 (0-3) GO1 IGBT15 GO2 GO3 GIN1 Gate Drive 1 GO2 GIN2 Gate Drive 2 GIN3 GO3 Gate Drive 3 4 GIN (0-3) LOGIC MAXI NOMI disabled NOMI LOGIC RSP2 Ign 2 VtNI VtNI NOMI Comparator RS2 VtMI VtMI MAXI Comparator Logic Buffer Logic Buffer VtMI MAXI disabled Logic Buffer Logic Buffer NOMI Comparator MAXI Comparator Logic Buffer Logic Buffer NOMI MAXI MAXI NOMI MAXI NOMI NOMI1 to uP MAXI1 to uP MAXI2 to uP NOMI2 to uP Note: For "child" input NOMI is for channel 1&3, input MAXI is for channel 0&2 Figure 10. V10 Mode LOW SIDE INJECTOR DRIVER The four open drain low side injector drivers are designed to control various automotive loads such as injectors, solenoids, lamps, relays and unipolar stepper motors. Each driver includes off and on state open load detection, short circuit protection and diagnostics. The injector drivers are individually controlled through the ON/OFF SPI input command Table 20 or parallel input pins DIN0 to DIN3. Serial and parallel control of the output state is determined by the logical OR of the SPI serial bit and the DINx parallel input pins. All four outputs are disabled when the OUTEN input pin is high regardless of the state of the SPI control bit or the state of the DINx pin. All four injector drivers are not affected by the selection of the gate driver's three modes of operation (Ignition Mode, General Purpose Mode, V10 mode). ON /OFF CONTROL COMMAND To program the individual output of the 33810 ON or OFF, a 16-bit serial stream of data is entered into the SI pin. The first 4 bits of the control word are used to identify the On / Off Command. Bit 0 through bit 3 of the ON/OFF Control Command turn ON or OFF the specific output driver. INJECTOR DRIVER FAULT COMMANDS Fault protection strategies for the injector drivers are programmed by the SPI LSD Fault Command. Bit 8 through 11 determine the type of short circuit protection to be used, bits 0 through 7 set the open load strategy. Short-circuit protection consists of three strategies. All strategies utilize current limiting as an active element to protect the output driver from failure.The TLIM and Timer options are used to enhance the short circuit protection strategy of the Injector drivers. The timer protection scheme uses a low duty cycle in the event of a short-circuit. The TLIM 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES protection circuit uses the junction temperature of the output driver to determine the fault. Both methods may be used together or individually. Table 18. Injector Driver (OUTx) Fault Operation Shutdn Retry Bit 11 1 TLIM Bit 10 0 Fault Timer Bit 9 X Operation During Short Fault Timer only, Outputs will retry on period OUT0-OUT3 = 60 s ON, ~10ms OFF 1 1 0 TLIM only, Outputs will retry on TLIM hysteresis. Timer and TLIM, Outputs will retry on period and driver temperature below threshold. OUT0-OUT3= 60 s ON, ~10ms OFF 0 0 X Timer only, Outputs will not retry on period OUT0-OUT3 = 60 s ON, OFF 0 1 0 TLIM only, Outputs will not retry on TLim hysteresis. Timer and TLIM, Outputs will not retry on period or TLIM. OUT0-OUT3 = 60 s ON, OFF TIMER PROTECTION The first protection scheme uses a low ON to OFF duty cycle to protect the output driver. The low duty cycle allows the device to cool so that the maximum junction temperatures are not exceeded. During a short condition, the device enters current limit. The driver will shutdown for short conditions lasting longer than the current limit timer (~60s) 1 1 1 TEMPERATURE LIMIT (TLIM) The second scheme senses the temperature of the individual output driver. During a short event the device enters current limit and will remain in current limit until the output driver temperature limit is exceeded (TLIM). At this point, the device will shutdown until the junction temperature falls below the hysteresis temperature value. The TLIM hysteresis value is listed in the previous specification tables. The third method combines both protection schemes into one. During a short event the device will enter current limit. The output driver will shutdown for short conditions lasting longer than the current limit timer. In the event that the output driver temperature is higher than maximum specified temperature the output will shutdown. The Shutdown/Retry bit allows the user to determine how the drivers will respond to each short circuit strategy. Table 18 provides fault operation for all three strategies. Outputs may be used in parallel to drive higher current loads provided the turn-off energy of the load does not exceed the energy rating of a single output driver (100mJ maximum). 0 1 1 OUTPUT DRIVER DIAGNOSTICS. Short to battery, Temperature Limit (TLIM) and open load faults are reported through the All Status Response message Table 21. OFF OPEN LOAD PULL-DOWN CURRENT ENABLE BITS An open load on the output driver is detected by the voltage level on the drain of the MOSFET in the off state. Internal to the device is a 75A pull-down current sink. In the event of an open load the drain voltage is pulled low. When the voltage crosses the threshold, and open load is detected. The pull-down current source may be disabled by bit 0 through bit 3 in the LSD Fault Command. With the driver off and the Off Open Load bit disabled, the Off Open Load fault status bit will be logic 0. ON OPEN LOAD ENABLE BITS The On State Open Load enable bit allows the user to determine an On State Open Load. When the On State Open Load bit disabled, the On State Fault bit is always logic 0. On Open Load is determined by monitoring the current through the OUTx MOSFET. In the ON state, currents less than 20mA to 200mA are considered open. 33810 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 19. InjectorDriver Diagnostics Program State Off State Open Load Pull Dwn On State Open Load En Bit Fault Output STB STG OPEN OUTx Batt Short Fault Fault Bits OUTx OFF Open Fault OUTx ON Fault Reported Open Fault temperature, calibration is required for an accurate time base. The calibration command should be used to update the device on a periodic basis. Driver On/Off SPI COMMAND SUMMARY The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 12 separate commands that are used to set operational parameters of device. The operational parameters are stored internally in 16 bit registers. Table 20 defines the commands and default state of the internal registers at POR. SPI commands may be sent to the device at any time in NORMAL STATE. Messages sent are acted upon on the rising edge of the CS input. 0 0 0 1 1 1 X X X X X X Off Off Off Off Off Off STB STG OPEN STB STG OPEN 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 No Fault No Fault No Fault No Fault Open Load Open Load X X X X X X 0 0 0 1 1 1 On On On On On On STB STG OPEN STB STG OPEN 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Short to Batt No Fault No Fault Short to Batt Open Load Open Load CLOCK CALIBRATION COMMAND In cases where an accurate time base is required, the user must calibrate the internal timers using the clock calibration command (refer to Table 20). After the 33810 device receives the calibration command, the device expects to receive a 32s logic [0] calibration pulse on the CS pin. The pulse is used to calibrate the internal clock. Any SPI message may be sent during the 32s calibration chip select. Because the oscillator frequency may shift up to 35% with . Table 20. SPI Command Message Set and Default State Command hex Read Registers Command All Status Command SPI Check Command Mode Select Command 0 0 0 1 Control Address Bits 15 0 0 0 0 14 0 0 0 0 13 0 0 0 0 12 0 0 0 1 11 1 1 1 10 0 0 1 9 1 1 1 8 0 0 1 7 Command Bits 6 5 4 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 <0000> Internal Register Address 0 0 0 0 0 0 X 0 0 X <0000> IGN/GP Mode Select Set to IGN Mode <0> <0> V10 OVR/ En Undr Vtg Disab <0> <0> <0> <0> pwm3 pwm2 pwm1 pwm0 EN EN EN EN Disab Disab Disab Disab 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 20. SPI Command Message Set and Default State Command hex LSD Fault Command 2 Control Address Bits 15 0 14 0 13 1 12 0 11 10 9 8 X 7 Command Bits 6 5 4 3 2 1 0 <10X> LSD Flt Operation shutdn,Tlim,Timer Retry on timer and No Tlim <1> <1> <1> <1> <1> <1> <1> <1> OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0 ON ON ON ON OFF OFF OFF OFF Open Open Open Open Open Open Open Open Load Load Load Load Load Load Load Load Enabl Enabl Enabl Enabl Enabl Enabl Enabl Enabl <0000> GPGD OFF (ignored in Ignition Mode) <0000> OUTx Driver OFF Driver ON/OFF Command 0 = OFF, 1 = ON 3 0 0 1 1 X X X X Spark Command 4 0 1 0 0 <100> Max Dwell Timer MaxDwell Default=32ms (In Ignition Mode Only) <0> Max Dwell En Disab <0> <0> <0> <0> <11> Over Gain Soft Open Open lap Sel Shut 2ed Secondary Dwell Gain Dn En Clmp OSFLT Disab = 1 Disab Disab =100s <01> End Spark Threshold VPWR +5.5V <01> End Spark Thresh 4.0 s End Spark Filter 5 0 1 0 1 X X X X X X X X X X DAC Command 6 0 1 1 0 <1000> MAXI DAC Threshold MAXI=14A <011> Short to Batt VFB3 Vth = 2.0V <011> Short to Batt tFB3 Timer = 240s <100> Overlap Setting Overlap 50% <01010> NOMI DAC Threshold NOMI=5.5A <011> Short to Batt VFB0 Vth = 2.0V <011> Short to Batt tFB0 Timer = 240s GPGD Short Threshold Voltage Command GPGD Short Duration Timer Command GPGD Fault Operation Select Command PWM0 to PWM3 Freq & DC Command 7 0 1 1 1 <011> Short to Batt VFB2 Vth = 2.0V <011> Short to Batt tFB2 Timer = 240s X X <011> Short to Batt VFB1 Vth = 2.0V <011> Short to Batt tFB1 Timer = 240s X X 8 1 0 0 0 9 1 0 0 1 <1111> Retry/Shutdown Bit Retry on Fault <00> PWMx address PWM0 X X X X X X X X X X <0000> Shutdown Drivers on MAXI Disabled A 1 0 1 0 <000> PWM Frequency 10Hz X X X X X X X X X X X X X X X X X X X X X X X X X <0000000> PWM Duty Cycle 0% Duty Cycle X X X X X X X X X X X X X X X X X X X X X X X X X INVALID COMMAND INVALID COMMAND INVALID COMMAND Clock Calibration Command INVALID COMMAND B C D E F 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 33810 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SPI RESPONSE REGISTERS Fault reporting is accomplished through the SPI interface. All logic [1]s received by the MCU via the SO pin indicate faults. All logic [0]s received by the MCU via Pin indicate no Table 21. SPI Response Messages 15 Next SO Response to: SPI Check Command Next SO Response to Reset COR HEX1 to HEX A Commands and Read All Status Command ALL STATUS RESPONSE Next SO Response to READ REGISTER COMMAND Address <0000> All Status Register 0 = No Fault, 1 = Fault Address <0001> OUT1, OUT0 Fault Register 0 = No Fault, 1 = Fault Address <0010> OUT3, OUT2 Fault Register 0 = No Fault, 1 = Fault Address <0011> GPGD Mode Fault Register 0 = No Fault, 1 = Fault 15 14 SOR NMF 0 14 0 13 0 12 0 11 1 10 1 faults. Timing between two write words must be greater than the fault timer to allow adequate time to sense and report the proper fault status. . 9 0 8 1 7 0 6 0 5 0 4 0 3 1 2 0 1 1 0 0 IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0 Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset COR SOR NMF IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0 Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault 0 0 0 0 OUT1 OUT1 OUT1 OUT1 OUT0 OUT0 OUT0 OUT0 TLIM Batter OFF ON TLIM Batter OFF ON Fault y Open Open Fault y Open Open Short Fault Fault Short Fault Fault Fault Fault OUT3 OUT3 OUT3 OUT3 OUT2 OUT2 OUT2 OUT2 TLIM Batter OFF ON TLIM Batter OFF ON Fault y Open Open Fault y Open Open Short Fault Fault Short Fault Fault Fault Fault GP3 Short Circuit Fault GP3 Open Load Fault GP2 Short Circuit Fault GP2 Open Load Fault GP1 Short Circuit Fault GP1 Open Load Fault GP0 Short Circuit Fault GP0 Open Load Fault Reset COR OVER LOW Voltage Voltage Reset COR OVER LOW Voltage Voltage 0 0 0 0 Reset COR OVER LOW Voltage Voltage 0 0 0 0 Address <0100> Reset COR OVER LOW IGN3 IGN3 IGN3 IGN2 IGN2 IGN Mode Fault Register Voltage Voltage MAXI Max Open MAXI Max 0 = No Fault, 1 = Fault Fault Dwell Secon Fault Dwell Fault d Fault Fault Address <0101> Reset COR OVER LOW Mode Command Register Voltage Voltage Address <0110> LSD Fault Command Register Address <0111> Drvr ON/OFF Command Reg Reset COR IGN/GP Mode Select V10 En IGN2 IGN1 IGN1 IGN1 IGN0 IGN0 IGN0 Open MAXI Max Open MAXI Max Open Secon Fault Dwell Secon Fault Dwell Secon d Fault d Fault d Fault Fault Fault OVR Vtg X X PWM PWM PWM PWM 3 2 1 0 EN EN EN EN OUT3 OFF Open Load OUT2 OFF Open Load OUT1 OFF Open Load OUT0 OFF Open Load OVER LOW LSD Flt Operation Voltage Voltage shutdn,Tlim,Timer X OUT3 OUT2 OUT1 OUT0 ON ON ON ON Open Open Open Open Load Load Load Load GPGD(19) Reset COR OVER LOW Voltage Voltage X X X X OUTx Driver(19) Address <1000> Reset COR OVER LOW Spark Command Register Voltage Voltage Max Dwell Timer MaxDwell Max Over Gain Soft Open Dwell lap Sel Shut 2ed En Dwell Dn En Clmp Open Secondary End Spark Threshold Notes 19. These bits refer to command On or Off state in the command registers, not the state of the respective output lines. These bits are not to be confused with the ignition mode state which is controlled only by the parallel inputs and their state is not reflected in these bits. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 21. SPI Response Messages Address <0101> End Spark filter Register Reset COR OVER under Voltage voltage X X X X X X X X X X End spark Filter Address <1010> Reset COR OVER LOW DAC Command Register Voltage Voltage MAXI DAC Threshold Overlap Setting NOMI DAC Threshold Short to Batt VFB0 Address <1011> Reset COR OVER LOW Short to Batt VFB3 GPGD FBx Short to Voltage Voltage Battery Threshold Voltage Register Address <1100> GPGD FBx Short to Battery Threshold Timer Register Address <1101> GPGD Fault Operation Register Address <1110> PWM Freq&DC Register (last channel programmed) Address <1111> Revision ID, Trim, Clock Cal. Legend COR = Command Out of Range SOR = Supply Out of Range Reset COR OVER LOW Voltage Voltage Short to Batt tFB3 Short to Batt VFB2 Short to Batt VFB1 Short to Batt tFB2 Short to Batt tFB1 Short to Batt tFB0 Reset COR OVER LOW Voltage Voltage OVER LOW Voltage Voltage Retry/Shutdown Bit X X X X Shutdown Drivers on IMAX Reset COR PWMx address PWM Frequency PWM Duty Cycle Reset COR OVR LOW Vtg Voltage REV 3 2 ID 1 0 X X CAL Too HI CAL Too LOW X X TRIM TRIM Parity Lock Error Out NMF = Set When Faults Occur on V10 Mode MAXI and NOMI Inputs and V10 Mode Ignition Driver are OFF. 33810 30 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. EK (Pb-FREE) SUFFIX 32-PIN 98ARL10543D ISSUE B 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 31 PACKAGING PACKAGE DIMENSIONS . EK (Pb-FREE) SUFFIX 32-PIN 98ARL10543D ISSUE B 33810 32 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 3.0 4.0 DATE 10/2007 2/2008 DESCRIPTION OF CHANGES * Initial Release * Fixed several typos throughout document * Changed Static Electrical Characteristics, Table 3, Digital Interface, OUT_EN Leakage Current to VDD, maximum from 10 to 50A. * Reworded not to Table 15. * Added Table 16 back (it was inadvertently deleted. * Added "Ignition &" to tile in Table 4. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 33 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2006 - 2008. All rights reserved. MC33810 Rev. 4.0 2/2008 |
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